View ENA2110_8282518.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

82912hkpc 018-08-0097 no. a2110-1/22 http://onsemi.com semiconductor components industries, llc, 2013 june, 2013 stk672-523-e overview the stk672-523-e is a hybrid ic for use as a unipolar, 2-phase stepping motor driver with pwm current control. applications ? office photocopiers, printers, etc. features ? the motor speed can be controlled by the frequency of an external clock signal. ? 2-phase excitation or 1-2 phase excitation is selected according to switching the state of the mode pin (low or high). ? the phase is maintained even if the excitatio n mode is switched in the middle of operation. ? the direction of rotation can be changed by applying a high or low signal to the cwb pin used to select the direction of rotation. ? supports schmitt input for 2.5v high level input. ? incorporating a current detection resistor (0.33 : resistor tolerance 2%), motor curr ent can be set using two external resistors. ? equipped with an enable pin that, during clock input, allows motor output to be cut-off and resumed later while maintaining the same excitation timing. ordering number : ENA2110 thick-film hybrid ic 2-phase stepping motor driver
stk672-523-e no. a2110-2/22 specifications absolute maximum ratings at tc = 25 c parameter symbol conditions ratings unit maximum supply voltage 1 v cc max no signal 52 v maximum supply voltage 2 v dd max no signal -0.3 to +7.0 v input voltage v in max logic input pins -0.3 to +7.0 v output current 1 i op max 10 a 1 pulse (resistance load) 5 a output current 2 i oh max v dd =5v, clock 200hz 1.4 a allowable power dissipation pd max with an arbitrarily large heat sink. per mosfet 10.2 w operating substrate temperature tc max 105 c junction temperature tj max 150 c storage temperature tstg -40 to +125 c allowable operating ranges at ta=25 c parameter symbol conditions ratings unit operating supply voltage 1 v cc with signals applied 10 to 42 v operating supply voltage 2 v dd with signals applied 5 5% v input high voltage v ih pins 8, 9, 10, 11, 12 2.5 to v dd v input low voltage v il pins 8, 9, 10, 11, 12 0 to 0.6 v output current 1 i oh 1 tc=105 c, clock 200hz, continuous operation, duty=100% 1.0 a output current 2 i oh 2 tc=80 c, clock 200hz, continuous operation, duty=100%, see the motor current (i oh ) derating curve 1.1 a clock frequency f cl minimum pulse width: at least 10 s 0 to 50 khz phase driver withstand voltage v dss i d =1ma (tc=25 c) 100min v recommended operating substrate temperature tc no condensation 0 to 105 c recommended vref range vref tc=105 c 0.14 to 1.62 v input rise and fall slew rate tr/tf 2.6max v electrical characteristics at tc=25 c, v cc =24v, v dd =5.0v parameter symbol conditions min typ max unit v dd supply current i cco pin 6 current clock=gnd 3.1 7 ma output average current ioave r/l=3 /3.8mh in each phase 0.148 0.164 0.180 a fet diode forward voltage vdf if=1a (r l =23 ) 1.2 1.8 v output saturation voltage vsat r l =23 0.61 0.85 v input high voltage v ih pins 8, 9, 10, 11, 12 2.5 v input low voltage v il pins 8, 9, 10, 11, 12 0.6 v input leak current i il pins 8, 9, 10, 11, 12=gnd and 5v 10 a vref input bias current i ib pin 7 =1.0v 204 216 a pwm frequency fc 35 45 55 khz notes: a fixed-voltage power supply must be used. stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
stk672-523-e no. a2110-3/22 package dimensions unit:mm (typ) derating curve of motor current, i oh, vs. stk672-523-e operating s ubstrate temperature, tc notes ? the current range given above represents conditions wh en output voltage is not in the avalanche state. ? if the output voltage is in the avalanche state, see the allowable avalanche energy for stk672-5** series hybrid ics given in a separate document. ? the operating substrate temperature, tc, given abov e is measured while the motor is operating. because tc varies depending on the am bient temperature, ta, the value of i oh , and the continuous or intermittent operation of i oh , always verify this value using an actual set. ? tc must measure surface metal temperature on rear side center of this device. i oh -tc operating substrate temperature, tc - c motor current, i oh - a 1.6 1.2 1.4 0.2 0.4 0.6 0.8 1.0 0 080 20 40 60 100 70 10 30 50 90 110 200hz 2 phase excitation hold mode 11 2.0=22.0 26.0 32.5 8.5 2.0 0.5 0.4 2.9 4.0 1.0 112
stk672-523-e no. a2110-4/22 block diagram sample application circuit *r02 is normally open. chopper circuit phase excitation signal generator excitation mode selection phase advance counter v ss ci bi ai fbb fbo fab fao bb b ab a gnd f1 f2 f3 f4 r1 r2 v dd v dd (5v) mode clock cwb enable vref resetb 7 12 11 10 9 8 6 1 4 5 2 3 stk672-523-e clock mode cwb + 6 9 8 10 12 11 7 1 4 5 2 3 resetb a ab b bb vref r01 r03 r02 gnd p.gnd v cc 24v c01 at least 100 f 2 phase stepping motor r04 + c02 10 f d1 v dd (5v) enable
stk672-523-e no. a2110-5/22 precautions [gnd wiring] ? to reduce noise on the 5v system, be sure to place the gnd of c01 in the circuit given above as close as possible to pin 1 of the hybrid ic. also, the gnd side of ro2 must be directly wired from p.gnd terminal pin 1 in order to accurately set the current. [input pins] ? insert resistor ro3 (47 to 100 ) so that the discharge energy from capacitor co2 is not directly applied to the cmos ic in this hybrid device. if the diode d1 has vf characteristi cs with vf less than or eq ual to 0.6v (when if = 0.1a), this will be smaller than the cmos ic input pin diode vf. if this is the case ro3 may be replaced with a short without problem. ? apply 2.5v high level input to pins 8, 9, 10, 11, and 12. ? if v dd is being applied, use care that each input pin does not apply a negative voltage less than -0.3v to p.gnd, pin 1, and do not apply a voltage greater than or equal to v dd voltage. ? since the input pins do not have built-in pull-up resistors, wh en the open-collector type pins 8, 9, 10, 11, and 12 are used as inputs, a 10 to 47k pull-up resistor (to v dd ) must be used. at this time, use a device for the open collector driver that has output current specifications that pull the voltage down to less than 0.6v at low level. [current setting vref] ? in consideration of the specifications of the vref input bias current, i ib , a resistance from several k to 100k is recommended for ro1. ? if the motor current is temporarily reduce d, the circuit given below (stk672-523: i oh >0.09a) is recommended. ? although the driver is equipped with a fixed current control function, it is not equipped with an overcurrent protection function to ensure that the current does not exceed the maximum output current, i oh max. if vref is mistakenly set to a voltage that exceeds i oh max, the driver will be damaged by overcurrent. 5v ro1 ro2 r3 5v ro1 ro2 r3 vref vref
stk672-523-e no. a2110-6/22 ? motor current peak value i oh setting ? when ro2 is open i oh = [vref 1k/(1k+3.9k)] rs= (vref 4.9) rs the values 1k and 3.9k repres ent internal driver resistance values, while rs represents the internal driver current detection resistance. vref= (4.9k (4.9k+ro1)) 5v (or 3.3v) =i oh 4.9 rs the value 4.9k represents the series resistance valu e of the internal driver values of 1k and 3.9k. ? if ro2 is connected i oh = [vref 1k/ (1k+3.9k)] rs= (vref 4.9) rs the values 1k and 3.9k repres ent the internal driver resistance values, while rs represents the in ternal driver current detection resistance. vref= (r0x (ro1+r0x)) 5v (or 3.3v) =i oh 4.9 rs = [(4.9k ro2) ((4.9k ro2) +ro1 (4.9k+ro2))] 5v(or 3.3v) r0x= (4.9k ro2) (4.9k+ro2) rs represents the current detection resistance inside the hi c, while the value 4.9k in th e formula above represents the internal resistance valu e of the vref pin. rs=0.11 when using the stk672-543-e rs=0.165 when using the stk672-533-e rs=0.33 when using the stk672-523-e [smoke emission precuations] if any of the output pins 2, 3, 4, and 5 is held open, the electrical stress onto the driver due to the inductive energy accumulated in the motor could cause short-circuit followed by permanent damage to the in ternal mosfet. as a result, the stk672-523-e may give rise to emit smoke. input pin functions pin name pin no. function input conditions when operating clock 9 reference clock for motor phase current sw itching operates on the rising edge of the signal mode 8 excitation mode selection low: 2-phase excitation high: 1-2 phase excitation cwb 10 motor direction switching low: cw (forward) high: ccw (reverse) resetb 11 system reset and a, ab , b, and bb outputs cutoff. applications must apply a reset signal for at least 10 s when v dd is first applied. a reset is applied by a low level enable 12 the a, ab, b, and bb outputs are turned off, and after operation is restored by returning the enable pin to the high level, operation continues with the same excitation timing as before the low-level input. the a, ab, b, and bb outputs are turned off by a low- level input. (1) a simple reset function is formed from d1, co2, ro3, and ro4 in this application circuit. with the clock input held low, when the 5v supply voltage is brought up a reset is applied if the motor output phases a and bb are driven. if the 5v supply voltage rise time is slow (over 50ms), the motor output phases a and bb may not be driven. increase the value of the capacitor co 2 and check circuit operation again. (2) see the timing chart for the concrete details on circuit operation. i oh 0
stk672-523-e no. a2110-7/22 timing charts 2-phase excitation 1-2 phase excitation resetb v dd mode cwb clock enable fao fab fbo fbb resetb v dd mode cwb clock enable fao fab fbo fbb
stk672-523-e no. a2110-8/22 1-2 phase excitation 2-phase excitation switch to 1-2 phase excitation resetb v dd mode cwb clock enable fao fab fbo fbb resetb v dd mode cwb clock enable fao fab fbo fbb
stk672-523-e no. a2110-9/22 1-2-phase excitation switch to 2 phase excitation resetb v dd mode cwb clock enable fao fab fbo fbb
stk672-523-e no. a2110-10/22 1-2 phase excitation (enable) 1-2 phase excitation (hold operation results during fixed clock) resetb v dd mode cwb clock enable fao fab fbo fbb hold operation resetb v dd mode cwb clock enable fao fab fbo fbb
stk672-523-e no. a2110-11/22 usage notes 1. stk672-523-e, stk672-533-e and stk672-543-e input signal functions and timing (all inputs have no internal pull-up resistor.) [resetb and clock (input signal timi ng when power is first applied)] as shown in the timing chart, a resetb signal input is requ ired by the driver to operate with the timing in which the f1 gate is turned on first. the resetb signal timing must be set up to have a width of at least 4 s, as shown below. the capacitor co2, and the resistors ro3 and ro4 in the app lication circuit form simple reset circuit that uses the rc time constant rising time. however, when designing the resetb input based on v ih levels, the application must have the timing shown in figure. figure 1 resetb and clock signals input timing [clock (phase switching clock)] ? input frequency: dc to 50khz ? minimum pulse width: 10 s ? signals are read on the rising edge. [cwb (motor direction setting)] the direction of rotation is switched by setting cwb to 1 (high) or 0 (low). see the timing charts for details on the operation of the outputs. note: the state of the cwb input must not be changed during the 4 s period before and after the rising edge of the clock input. [enable (controls forced off for a, ab, b, and selects bb and selects operation/hold mode of the hybrid ic)] enable=1: normal operation enable=0: outputs a, ab, b, an d bb forced to the off state. if, during the state where clock signal input is provid ed, the enable pin is set to 0 and then is later restored to the 1 state, the ic will resume opera tion with the excitation timing continued from before the point enable was set to 0. enable must be initially set high for input as shown in the timing chart. [mode (excitation mode selection)] mode=0: 2-phase excitation mode=1: 1-2 phase excitation see the timing charts for details on output operation in these modes. note: the state of the mode input must not be changed during the 4 s period before and after the rising edge of the clock input. rise of the 5v supply voltage resetb signal input clock signal a t least 4
stk672-523-e no. a2110-12/22 [configuration of each input pin] input pins: pin 8, 9, 10, 11, and 12 all input pins of this driver support sc hmitt input. typ specifications at tc = 25 c are given below. hysteresis voltage is 0.6v (viha-vila). input voltage specifications are as follows. v ih =2.5v min v il =0.6v max input pin: pin 7 5v v ss control ic viha when rising when falling 1.1vtyp vila 1.7vtyp input voltage 5v 1 7 1k /1% 3.9k /1% 0.1
stk672-523-e no. a2110-13/22 2. calculating stk672-523-e hic internal power loss the average internal power loss in each excitation mode of the stk672-523-e can be calculated from the following formulas. each excitation mode 2-phase excitation mode 2pdavex= (vsat+vdf) 0.5 clock i oh t2+0.5 clock i oh (vsat t1+vdf t3) 1-2 phase excitation mode 1-2pdavex= (vsat+vdf) 0.25 clock i oh t2+0.25 clock i oh (vsat t1+vdf t3) motor hold mode holdpdavex= (vsat+vdf) i oh vsat: combined voltage represented by the ron voltage drop+shunt resistor vdf: combined voltage represented by the mosfet body diode+shunt resistor clock: input clock (clock pin signal frequency) t1, t2, and t3 represent the waveforms shown in the figure below. t1: time required for the winding cu rrent to reach the set current (i oh ) t2: time in the constant current control (pwm) region t3: time from end of phase input signal until inverse current regeneration is complete motor com current waveform model t1= (-l/(r+0.61)) ln (1-((r+0.61)/v cc ) i oh ) t3= (-l/r) ln ((v cc +0.61)/(i oh r+v cc +0.61)) v cc : motor supply voltage (v) l: motor inductance (h) r: motor winding resistance ( ) i oh : motor set output current crest value (a) relationship of clock, t1, t2, and t3 in each excitation mode 2-phase excitation mode: t2= (2/clock) - (t1+t3) 1-2 phase excitation mode: t2= (3/clock) -t1 for vsat and vdf, be sure to substitute values from the graphs of vsat vs. i oh and vdf vs. i oh while the set current value is i oh . then, determine whether a heat sink is re quired by comparing with the graph of tc vs. pd based on the average hic power loss calculated. when designing a heat sink, refer to the section ?thermal design? found on the next page. the average hic power loss, pdav, described above does not have the avalanche?s loss. to include the avalanche?s loss, be sure to add equation (2), ?stk672-5** allowable avalanche energy valu e? to pdav above. when using this ic without a fin always check for temperature increases in the set, because the hic substrate temper ature, tc, varies due to effects of convection around the hic. i oh 0a t1 t2 t3
stk672-523-e no. a2110-14/22 stk672-523-e output saturation voltage, vsat - output current, i oh stk672-523-e forward voltage, vdf -output current, i oh substrate temperature rise , tc (no heat sink) - internal average power dissipation, pdav 80 20 10 0 0 1.0 2.0 3.0 0.5 1.5 2.5 tc - pdav hybrid ic internal average power dissipation, pdav - w substrate temperature rise, tc - c 50 70 60 40 30 itf02566 vsat - i oh output current, i oh - a output saturation voltage, vsat - v 0 0.2 0.4 0.6 1.4 1.2 1.0 0.8 0.4 0.3 0.2 0.1 0 1.0 0.9 0.8 0.7 0.6 0.5 t c = 1 0 5 c 2 5 c vdf- i oh output current, i oh - a forward voltage, vdf - v 0 0.2 0.4 0.6 1.4 1.2 1.0 0.8 0.4 0.2 0 1.4 1.0 1.2 0.8 0.6 t c = 2 5 c 1 0 5 c
stk672-523-e no. a2110-15/22 3. stk672-523-e allowabl e avalanche energy value (1) allowable range in avalanche mode when driving a 2-phase stepping motor with constant current chopping using an stk672-5** series hybrid ic, the waveforms shown in figure 1 belo w result for the output current, i d , and voltage, v ds . figure 1 output current, i d , and voltage, v ds , waveforms 1 of the stk672-5** series when driving a 2-phase stepping motor with constant current chopping when operations of the mosfet built into stk672-5** seri es ics is turned off for constant current chopping, the i d signal falls like the waveform shown in the figure above. at this time, the output voltage, v ds , suddenly rises due to electromagnetic induction generated by the motor coil. in the case of voltage that rises suddenly , voltage is restricted by the mosfet v dss . voltage restriction by v dss results in a mosfet avalanche. during avalanche operations, i d flows and the instantaneous energy at this time, eavl1, is represented by equation (1). eavl1=v dss iavl 0.5 tavl ------------------------------------------- (1) v dss : v units, iavl: a units, tavl: sec units the coefficient 0.5 in equation (1) is a constant required to convert the iavl triangle wave to a square wave. during stk672-5** series operations, the waveforms in the figure above repeat due to the constant current chopping operation. the allowable avalanche energy, eavl, is therefore represented by equation (2) used to find the average power loss, pavl, during avalanche mode multiplied by the chopping frequency in equation (1). pavl=v dss iavl 0.5 tavl fc ------------------------------------------- (2) fc: hz units (fc is set to the pwm frequency of 50khz.) for v dss , iavl, and tavl, be sure to actually operate th e stk672-5** series and substitute values when operations are observed using an oscilloscope. ex. if v dss =110v, iavl=1a, tavl=0.2 s when using a stk672-523-e driver, the result is: pavl=110 1 0.5 0.2 10 -6 50 10 3 =0.55w v dss =110v is a value actually measured using an oscilloscope. the allowable loss range for the allowable avalanche ener gy value, pavl, is shown in the graph in figure 3. when examining the avalanche energy, be sure to actually drive a motor and observe the i d , v dss , and tavl waveforms during operation, and then check that the result of calculating equation (2) falls within the allowable range for avalanche operations. v dss : voltage during avalanche operations i oh : motor current peak value iavl: current during avalanche operations tavl: time of avalanche operations v ds i d itf02557
stk672-523-e no. a2110-16/22 (2) i d and v dss operating waveforms in non-avalanche mode although the waveforms during avalanche mode are given in figure 1, sometimes an avalanche does not result during actual operations. factors causing avalanche are listed below. ? poor coupling of the motor?s phase coils (electromagnetic coupling of a phase and ab phase, b phase and bb phase). ? increase in the lead inductance of the harness caused by the circuit pattern of the p.c. board and motor. ? increases in v dss , tavl, and iavl in figure 1 due to an increase in the supply voltage from 24v to 36v. if the factors above are negligible, the waveforms shown in figure 1 become waveforms without avalanche as shown in figure 2. under operations shown in figure 2, avalanche does not occur and there is no need to consider the allowable loss range of pavl shown in figure 3. figure 2 output current, i d , and voltage, v ds , waveforms 2 of the stk672-5** series when driving a 2-phase stepping motor with constant current chopping figure 3 allowable loss range, pavl-i oh during stk672-523-e avalanche operations note: the operating conditions given above represent a loss when driving a 2-phase stepping motor with constant current chopping. because it is possible to apply 3.7w or more at i oh =0a, be sure to avoid using the mosfet body diode that is used to drive the motor as a zener diode. i oh : motor current peak value v ds i d itf02558 p a vl - i oh motor phase current, i oh - a average power loss in the avalanche state, p a vl - w 0 0.2 0.4 0.6 1.4 1.0 0.8 1.2 1 0 6 5 4 3 2 t c = 8 0 c 1 0 5 c
stk672-523-e no. a2110-17/22 4. thermal design [operating range in which a heat sink is not used] use of a heat sink to lower the operating substrate temperat ure of the hic (hybrid ic) is effective in increasing the quality of the hic. the size of heat sink for the hic varies depending on the magnitude of the average power loss, pdav, within the hic. the value of pdav increases as the output current in creases. to calculate pdav, refer to ?calculating internal hic loss for the stk672-523-e? in the specification document. calculate the internal hic loss, pdav, assuming repeat operation such as shown in figure 1 below, since conduction during motor rotation and off time both exist during actual motor operations. figure 1 motor current timing t1: motor rotation operation time t2: motor hold operation time t3: motor current off time t2 may be reduced, depending on the application. t0: single repeated motor operating cycle i o 1 and i o 2: motor current peak values due to the structure of motor windings, the phase current is a positive and negative current with a pulse form. note that figure 1 presents the concepts here, and that the on/off duty of the actual signals will differ. the hybrid ic internal average power dissipation pdav can be cal culated from the following formula. pdav= (t1 p1+t2 p2+t3 0) t0 ---------------------------- (i) (here, p1 is the pdav for i o 1 and p2 is the pdav for i o 2) if the value calculated using equation (i) is 1.5w or less, and the ambient temperature, ta, is 60 c or less, there is no need to attach a heat sink. refer to figure 2 for operating substrate temperature data when no heat sink is used. [operating range in which a heat sink is used] although a heat sink is attached to lower tc if pdav in creases, the resulting size can be found using the value of c-a in equation (ii) below and the graph depicted in figure 3. c-a= (tc max-ta) pdav ---------------------------- (ii) tc max: maximum operating substrate temperature =105 c ta: hic ambient temperature although a heat sink can be designed based on equations (i) and (ii) above, be sure to mount the hic in a set and confirm that the substrate temperature, tc, is 105 c or less. the average hic power loss, pdav, described above represents the power loss when there is no avalanche operation. to add the loss during avalanche operations, be sure to add equation (2), ?allowa ble stk672-5** avalanche energy value?, to pdav. i o 1 i o 2 -i o 1 0a t1 t2 t3 t0 motor phase current (sink side)
stk672-523-e no. a2110-18/22 figure 2 substrat e temperature rise, tc - internal average power dissipation, pdav figure 3 heat sink area (board thickness: 2mm) - c-a 80 20 10 0 0 1.0 2.0 3.0 0.5 1.5 2.5 tc - pdav hybrid ic internal average power dissipation, pdav - w substrate temperature rise, tc - c 50 70 60 40 30 itf02566 2 1.0 2 100 7 10 35 2 7 35 1000 c-a - s heat sink area, s - cm 2 heat sink thermal resistance, c-a - c/w 5 100 3 10 7 2 5 3 7 w i t h n o s u r f ace f i n i s h w i t h a f l a t b l a c k s u r f a c e f i n i s h itf02554
stk672-523-e no. a2110-19/22 5. changes in motor state when switchi ng excitation with stk672-5** series example 1: switching from 2-phase to 1-2 phase excitation motor status is maintained when the excitation mode (mode) is switched during motor rotation. because clock cannot be detected when the interval between the rise in the mode and clock signals is 5 s or less, the mode may not change for one clock cycle. the solid arrows indicate 2-phase excitation, an d dashed arrows indicate 1-phase excitation. (1) (2) (3) (4) (5) (6) (7) clock fao fab fb0 fbb mode a a bb
stk672-523-e no. a2110-20/22 example 2: switching from 1-2 phase to 2-phase excitation motor status is maintained when the excitation mode (mode) is switched during motor rotation. because clock cannot be detected when the interval betw een the rise in the mode signal and clock signal is 5 s or less, the mode may not change for one clock cycle. the solid arrows indicate 2-phase excitation, an d dashed arrows indicate 1-phase excitation. (1) (2) (3) (4) (5) (6) (7) fao fab fb0 fbb clock mode a a b b
stk672-523-e no. a2110-21/22 ex.3: changeover from 1-2 phase to 2-phase excitation this driver stabilizes motor phas e performance at changeover excitation mode during motor motion. this driver is not able to detect clock rising edge, if the time between clock and mode rising edge was less than 4 s. therefore, motor phase performance doesn?t change in 1 clock cycle. the solid arrows indicate 2-phase excitation, an d dashed arrows indicate 1-phase excitation. (1) (2) (3) (4) (5) (6) (7) fao fab fb0 fbb clock mode a a b b
stk672-523-e no. a2110-22/22 ps on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

▲Up To Search▲

Price & Availability of ENA2110

	To Download ENA2110 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .